Semiconductor devices are manufactured by forming active regions in a semiconductor substrate, depositing various insulating, conductive, and semiconductive layers over the substrate, and patterning them in sequential steps. The upper or last-formed layers of the semiconductor device typically comprise metallization layers. The metallization layers typically comprise one or more layers of metal interconnect having conductive lines disposed within an insulating material and may provide connections to underlying active regions and connections within and over the substrate. Integrated circuit chips may be attached to a lead frame and then packaged in a ceramic or plastic carrier.
As the cost of shrinking semiconductor devices continues to increase, however, alternative approaches, such as extending the integration of circuits into the third dimension or semiconductor substrate stacking are being explored. Two or more substrates are bonded together to form a three-dimensional structure. The active circuitry of the stacked substrates are coupled through one or more through substrate vias.
However, three-dimensional integration introduces many challenges to fabrication. One of the challenges in three-dimensional integration involves forming joints between the stacked substrates without forming additional shorts or leakage paths.
The through substrate vias used for coupling the substrates are insulated from the substrate by a dielectric layer. However, an electrical short between the underlying substrate and the through substrate via, for example, formed during the joint formation process can result in deleterious process yield and is hence undesirable.
Hence, what are needed are cost efficient means of stacking semiconductor substrates without compromising on process yield.